Atomic scale simulation of a junctionless silicon nanowire transistor

Lida Ansari; Baruch Feldman; Giorgos Fagas; Jean Pierre Colinge; James C. Greer

doi:10.1109/ULIS.2011.5757976

Atomic scale simulation of a junctionless silicon nanowire transistor

Lida Ansari, Baruch Feldman, Giorgos Fagas, Jean Pierre Colinge, James C. Greer

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

Abstract

We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, V_DS, and gate voltage, V_g. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.

Original language	English
Title of host publication	2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011
Pages	96-98
Number of pages	3
DOIs	https://doi.org/10.1109/ULIS.2011.5757976
Publication status	Published - 2011
Externally published	Yes
Event	2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011 - Cork, Ireland Duration: 14 Mar 2011 → 16 Mar 2011

Publication series

Name	2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011

Conference

Conference	2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011
Country/Territory	Ireland
City	Cork
Period	14/03/11 → 16/03/11

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ULIS.2011.5757976

Cite this

Ansari, L., Feldman, B., Fagas, G., Colinge, J. P., & Greer, J. C. (2011). Atomic scale simulation of a junctionless silicon nanowire transistor. In 2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011 (pp. 96-98). Article 5757976 (2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011). https://doi.org/10.1109/ULIS.2011.5757976

@inproceedings{d0a73925e3b544518194db9c912a1116,

title = "Atomic scale simulation of a junctionless silicon nanowire transistor",

abstract = "We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.",

author = "Lida Ansari and Baruch Feldman and Giorgos Fagas and Colinge, {Jean Pierre} and Greer, {James C.}",

note = "Copyright: Copyright 2011 Elsevier B.V., All rights reserved.; 2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011 ; Conference date: 14-03-2011 Through 16-03-2011",

year = "2011",

doi = "10.1109/ULIS.2011.5757976",

language = "English",

isbn = "9781457700903",

series = "2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011",

pages = "96--98",

booktitle = "2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011",

}

Ansari, L, Feldman, B, Fagas, G, Colinge, JP & Greer, JC 2011, Atomic scale simulation of a junctionless silicon nanowire transistor. in 2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011., 5757976, 2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011, pp. 96-98, 2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011, Cork, Ireland, 14/03/11. https://doi.org/10.1109/ULIS.2011.5757976

Atomic scale simulation of a junctionless silicon nanowire transistor. / Ansari, Lida; Feldman, Baruch; Fagas, Giorgos et al.
2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011. 2011. p. 96-98 5757976 (2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011).

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Atomic scale simulation of a junctionless silicon nanowire transistor

AU - Ansari, Lida

AU - Feldman, Baruch

AU - Fagas, Giorgos

AU - Colinge, Jean Pierre

AU - Greer, James C.

PY - 2011

Y1 - 2011

N2 - We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.

AB - We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.

UR - http://www.scopus.com/inward/record.url?scp=79957988885&partnerID=8YFLogxK

U2 - 10.1109/ULIS.2011.5757976

DO - 10.1109/ULIS.2011.5757976

M3 - Conference contribution

AN - SCOPUS:79957988885

SN - 9781457700903

T3 - 2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011

SP - 96

EP - 98

BT - 2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011

T2 - 2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011

Y2 - 14 March 2011 through 16 March 2011

ER -

Atomic scale simulation of a junctionless silicon nanowire transistor

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this