TY - GEN
T1 - Enabling Fine-Grained Dynamic Voltage and Frequency Scaling in SDSoC
AU - Jiang, Weixiong
AU - Yu, Heng
AU - Ha, Yajun
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/9
Y1 - 2019/9
N2 - Dynamic Voltage and Frequency Scaling (DVFS) has been extensively applied as a system-level methodology for energy optimization or temperature control. But current DVFS systems are mostly implemented on CPUs, DVFS working on FPGAs is limited. Moreover, all current DVFS systems available for FPGAs have either low scaling resolution or long reconfiguration time, and none of them is easy to reuse. In this paper, we develop a fast and efficient ZYNQ-based DVFS platform with high resolution and short reconfiguration time. In addition, we add the DVFS support to SDSoC and make it easier and quicker to build an ZYNQ system with DVFS features. We also apply our DVFS platform to a real-time semi-global matching (SGM) accelerator as a case study, and develop a DVFS policy to optimize its power consumption. Compared to the state-of-the-art, our DVFS platform saves 45% FFs and almost all LUTs, the voltage scaling time is 7ms and the frequency scaling time is 3 μ s, and time for one design iteration to add DVFS support is reduced from several hours to a few minutes. Compared to its unoptimized version, the SGM accelerator with our DVFS platform saves up to 46% energy.
AB - Dynamic Voltage and Frequency Scaling (DVFS) has been extensively applied as a system-level methodology for energy optimization or temperature control. But current DVFS systems are mostly implemented on CPUs, DVFS working on FPGAs is limited. Moreover, all current DVFS systems available for FPGAs have either low scaling resolution or long reconfiguration time, and none of them is easy to reuse. In this paper, we develop a fast and efficient ZYNQ-based DVFS platform with high resolution and short reconfiguration time. In addition, we add the DVFS support to SDSoC and make it easier and quicker to build an ZYNQ system with DVFS features. We also apply our DVFS platform to a real-time semi-global matching (SGM) accelerator as a case study, and develop a DVFS policy to optimize its power consumption. Compared to the state-of-the-art, our DVFS platform saves 45% FFs and almost all LUTs, the voltage scaling time is 7ms and the frequency scaling time is 3 μ s, and time for one design iteration to add DVFS support is reduced from several hours to a few minutes. Compared to its unoptimized version, the SGM accelerator with our DVFS platform saves up to 46% energy.
UR - http://www.scopus.com/inward/record.url?scp=85085175260&partnerID=8YFLogxK
U2 - 10.1109/SOCC46988.2019.1570558174
DO - 10.1109/SOCC46988.2019.1570558174
M3 - Conference contribution
AN - SCOPUS:85085175260
T3 - International System on Chip Conference
SP - 56
EP - 61
BT - Proceedings - 32nd IEEE International System on Chip Conference, SOCC 2019
A2 - Zhao, Danella
A2 - Basu, Arindam
A2 - Bayoumi, Magdy
A2 - Hwee, Gwee Bah
A2 - Tong, Ge
A2 - Sridhar, Ramalingam
PB - IEEE Computer Society
T2 - 32nd IEEE International System on Chip Conference, SOCC 2019
Y2 - 3 September 2019 through 6 September 2019
ER -