FPGA implementation of a configurable viterbi decoder for software radio receiver

Keyphrases

• Configurable Hardware 20%
• Convolutional Codes 40%
• Decoder 40%
• Digital Communication Systems 20%
• Field Programmable Gate Arrays 100%
• Forward Error Correction Codes 20%
• Hardware Platform 20%
• Highly Configurable 40%
• Low Power 20%
• Mentor Graphics 20%
• Microarray Technology 100%
• Processing Task 20%
• Proposed Design 40%
• Signal Processing 20%
• Software Defined Radio 60%
• Software Radio Receivers 100%
• Technology Advantage 20%
• Technology Implementation 100%
• VHDL Code 20%
• Viterbi Algorithm 20%
• Viterbi Decoder 100%
• Wireless Communication 20%
• Xilinx 20%
• Xilinx Virtex 20%

Computer Science

• Configurable Option 20%
• Convolutional Code 40%
• Error Correction Code 20%
• Field Programmable Gate Arrays 100%
• Forward Error Correction 20%
• Hardware Platform 20%
• Implementation Technology 100%
• Processing Task 20%
• Software Defined Radio 60%
• Viterbi Algorithm 20%
• Wireless Communication 20%

Engineering

• Convolutional Code 40%
• Correction Code 20%
• Digital Communication System 20%
• Field Programmable Gate Array Technology 100%
• Forward Error-Correction 20%
• Processing Task 20%
• Prototype 20%
• Software Defined Radio 60%
• Software Radio 100%
• Wireless Communication 20%